#include <assert.h>
#include <bl_common.h>
#include <debug.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <xlat_tables.h>
-#include "../hikey_def.h"
-
#define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
DDR_SIZE - DDR_SEC_SIZE, \
MT_DEVICE | MT_RW | MT_NS)
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include "../hikey_def.h"
+#include <hikey_def.h>
.globl plat_my_core_pos
.globl platform_mem_init
#include <emmc.h>
#include <errno.h>
#include <hi6220.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <string.h>
#include <tbbr/tbbr_img_desc.h>
#include "../../bl1/bl1_private.h"
-#include "hikey_def.h"
#include "hikey_private.h"
/*
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
/*******************************************************************************
#include <optee_utils.h>
#endif
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
#include <string.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
#include <errno.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <mmio.h>
#include <platform_def.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
+++ /dev/null
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __HIKEY_DEF_H__
-#define __HIKEY_DEF_H__
-
-#include <common_def.h>
-#include <tbbr_img_def.h>
-
-/* Always assume DDR is 1GB size. */
-#define DDR_BASE 0x0
-#define DDR_SIZE 0x40000000
-
-#define DEVICE_BASE 0xF4000000
-#define DEVICE_SIZE 0x05800000
-
-#define XG2RAM0_BASE 0xF9800000
-#define XG2RAM0_SIZE 0x00400000
-
-/* Memory location options for TSP */
-#define HIKEY_SRAM_ID 0
-#define HIKEY_DRAM_ID 1
-
-/*
- * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
- * regions
- * - Secure DDR (default is the top 16MB) used by OP-TEE
- * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
- * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
- * - Non-secure DDR (8MB) reserved for OP-TEE's future use
- */
-#define DDR_SEC_SIZE 0x01000000
-#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */
-
-#define DDR_SDP_SIZE 0x00400000
-#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
- DDR_SDP_SIZE)
-
-#define SRAM_BASE 0xFFF80000
-#define SRAM_SIZE 0x00012000
-
-/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
- * PL011 related constants
- */
-#define PL011_UART0_BASE 0xF8015000
-#define PL011_UART3_BASE 0xF7113000
-#define PL011_BAUDRATE 115200
-#define PL011_UART_CLK_IN_HZ 19200000
-
-#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
-#define HIKEY_USB_DESC_SIZE 0x00100000
-#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
-#define HIKEY_USB_DATA_SIZE 0x10000000
-#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
-#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
-#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
- HIKEY_FB_BUFFER_SIZE)
-#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
-
-#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
-#define HIKEY_USB_DESC_IN_SIZE 0x00040000
-#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
- HIKEY_USB_DESC_IN_SIZE)
-#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
-#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
- HIKEY_USB_DESC_EP0_OUT_SIZE)
-#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
-
-#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
-#define HIKEY_MMC_DESC_SIZE 0x00100000
-
-/*
- * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
- * and eMMC driver. Since it could avoid to memory copy.
- * So this SRAM region is used twice. First, it's used in BL1 as temporary
- * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
- * needs to be clear before used in BL2.
- */
-#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
-#define HIKEY_MMC_DATA_SIZE 0x20000000
-#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
-#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
-#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
-#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
- HIKEY_BL1_MMC_DESC_SIZE)
-#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
-
-#define EMMC_BASE 0
-#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20))
-#define HIKEY_FIP_MAX_SIZE (8 << 20)
-#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
-#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
-#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
-#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
-
-/*
- * GIC400 interrupt handling related constants
- */
-#define IRQ_SEC_PHY_TIMER 29
-#define IRQ_SEC_SGI_0 8
-#define IRQ_SEC_SGI_1 9
-#define IRQ_SEC_SGI_2 10
-#define IRQ_SEC_SGI_3 11
-#define IRQ_SEC_SGI_4 12
-#define IRQ_SEC_SGI_5 13
-#define IRQ_SEC_SGI_6 14
-#define IRQ_SEC_SGI_7 15
-#define IRQ_SEC_SGI_8 16
-
-#endif /* __HIKEY_DEF_H__ */
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <debug.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <hisi_sram_map.h>
#include <psci.h>
#include <sp804_delay_timer.h>
-#include "hikey_def.h"
-
#define CORE_PWR_STATE(state) \
((state)->pwr_domain_state[MPIDR_AFFLVL0])
#define CLUSTER_PWR_STATE(state) \
--- /dev/null
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HIKEY_DEF_H__
+#define __HIKEY_DEF_H__
+
+/* Always assume DDR is 1GB size. */
+#define DDR_BASE 0x0
+#define DDR_SIZE 0x40000000
+
+#define DEVICE_BASE 0xF4000000
+#define DEVICE_SIZE 0x05800000
+
+/* Memory location options for TSP */
+#define HIKEY_SRAM_ID 0
+#define HIKEY_DRAM_ID 1
+
+/*
+ * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
+ * regions
+ * - Secure DDR (default is the top 16MB) used by OP-TEE
+ * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
+ * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
+ * - Non-secure DDR (8MB) reserved for OP-TEE's future use
+ */
+#define DDR_SEC_SIZE 0x01000000
+#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */
+
+#define DDR_SDP_SIZE 0x00400000
+#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
+ DDR_SDP_SIZE)
+
+#define SRAM_BASE 0xFFF80000
+#define SRAM_SIZE 0x00012000
+
+/*
+ * PL011 related constants
+ */
+#define PL011_UART0_BASE 0xF8015000
+#define PL011_UART3_BASE 0xF7113000
+#define PL011_BAUDRATE 115200
+#define PL011_UART_CLK_IN_HZ 19200000
+
+#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
+#define HIKEY_USB_DESC_SIZE 0x00100000
+#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
+#define HIKEY_USB_DATA_SIZE 0x10000000
+#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
+#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
+#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
+ HIKEY_FB_BUFFER_SIZE)
+#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
+
+#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
+#define HIKEY_USB_DESC_IN_SIZE 0x00040000
+#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
+ HIKEY_USB_DESC_IN_SIZE)
+#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
+#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
+ HIKEY_USB_DESC_EP0_OUT_SIZE)
+#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
+
+#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
+#define HIKEY_MMC_DESC_SIZE 0x00100000
+
+/*
+ * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
+ * and eMMC driver. Since it could avoid to memory copy.
+ * So this SRAM region is used twice. First, it's used in BL1 as temporary
+ * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
+ * needs to be clear before used in BL2.
+ */
+#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
+#define HIKEY_MMC_DATA_SIZE 0x20000000
+#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
+#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
+#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
+#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
+ HIKEY_BL1_MMC_DESC_SIZE)
+#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
+
+#define EMMC_BASE 0
+#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20))
+#define HIKEY_FIP_MAX_SIZE (8 << 20)
+#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
+#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
+#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
+#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
+
+/*
+ * GIC400 interrupt handling related constants
+ */
+#define IRQ_SEC_PHY_TIMER 29
+#define IRQ_SEC_SGI_0 8
+#define IRQ_SEC_SGI_1 9
+#define IRQ_SEC_SGI_2 10
+#define IRQ_SEC_SGI_3 11
+#define IRQ_SEC_SGI_4 12
+#define IRQ_SEC_SGI_5 13
+#define IRQ_SEC_SGI_6 14
+#define IRQ_SEC_SGI_7 15
+#define IRQ_SEC_SGI_8 16
+
+#endif /* __HIKEY_DEF_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HIKEY_LAYOUT_H
+#define __HIKEY_LAYOUT_H
+
+/*
+ * Platform memory map related constants
+ */
+#define XG2RAM0_BASE 0xF9800000
+#define XG2RAM0_SIZE 0x00400000
+
+/*
+ * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
+ */
+#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
+#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
+#define BL1_XG2RAM0_OFFSET 0x1000
+
+/*
+ * BL1 specific defines.
+ *
+ * Both loader and BL1_RO region stay in SRAM since they are used to simulate
+ * ROM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL1_RO +
+ * ++++++++++ 0xF981_0000
+ * + BL1_RW +
+ * ++++++++++ 0xF989_8000
+ */
+#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
+#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
+#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
+#define BL1_RW_SIZE (0x00088000)
+#define BL1_RW_LIMIT (0xF9898000)
+
+/*
+ * Non-Secure BL1U specific defines.
+ */
+#define NS_BL1U_BASE (0xf9818000)
+#define NS_BL1U_SIZE (0x00010000)
+#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
+
+/*
+ * BL2 specific defines.
+ *
+ * Both loader and BL2 region stay in SRAM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL2 +
+ * ++++++++++ 0xF981_8000
+ */
+#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
+#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
+
+/*
+ * SCP_BL2 specific defines.
+ * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
+ * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
+ * predefined separated buffers.
+ */
+#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
+#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
+#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
+
+/*
+ * BL31 specific defines.
+ */
+#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
+#define BL31_LIMIT (0xF9898000)
+
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM or SRAM.
+ */
+#define BL32_SRAM_BASE BL31_LIMIT
+#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
+
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#ifdef SPD_opteed
+/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
+#endif
+
+#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
+#define BL32_BASE BL32_SRAM_BASE
+#define BL32_LIMIT BL32_SRAM_LIMIT
+#else
+#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
+#endif
+
+/* BL32 is mandatory in AArch32 */
+#ifndef AARCH32
+#ifdef SPD_none
+#undef BL32_BASE
+#endif /* SPD_none */
+#endif
+
+#endif /* !__HIKEY_LAYOUT_H */
#define __PLATFORM_DEF_H__
#include <arch.h>
-#include "../hikey_def.h"
+#include <common_def.h>
+#include <hikey_def.h>
+#include <hikey_layout.h> /* BL memory region sizes, etc */
+#include <tbbr_img_def.h>
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
#define PLAT_ARM_GICH_BASE 0xF6804000
#define PLAT_ARM_GICV_BASE 0xF6806000
-
-/*
- * Platform memory map related constants
- */
-
-/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
- * BL1 specific defines.
- *
- * Both loader and BL1_RO region stay in SRAM since they are used to simulate
- * ROM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL1_RO +
- * ++++++++++ 0xF981_0000
- * + BL1_RW +
- * ++++++++++ 0xF989_8000
- */
-#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
-#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
-#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
-#define BL1_RW_SIZE (0x00088000)
-#define BL1_RW_LIMIT (0xF9898000)
-
-/*
- * BL2 specific defines.
- *
- * Both loader and BL2 region stay in SRAM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL2 +
- * ++++++++++ 0xF981_8000
- */
-#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
-#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
-
-/*
- * SCP_BL2 specific defines.
- * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
- * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
- * predefined separated buffers.
- */
-#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
-#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
-#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
-
-/*
- * BL31 specific defines.
- */
-#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
-#define BL31_LIMIT (0xF9898000)
-
-/*
- * BL3-2 specific defines.
- */
-
-/*
- * The TSP currently executes from TZC secured area of DRAM or SRAM.
- */
-#define BL32_SRAM_BASE BL31_LIMIT
-#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
-
-#define BL32_DRAM_BASE DDR_SEC_BASE
-#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
-
-#ifdef SPD_opteed
-/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
-#endif
-
-#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
-#define BL32_BASE BL32_DRAM_BASE
-#define BL32_LIMIT BL32_DRAM_LIMIT
-#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
-#define BL32_BASE BL32_SRAM_BASE
-#define BL32_LIMIT BL32_SRAM_LIMIT
-#else
-#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
-#endif
-
-/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
-#ifdef SPD_none
-#undef BL32_BASE
-#endif /* SPD_none */
-#endif
-
-#define NS_BL1U_BASE (0xf9818000)
-#define NS_BL1U_SIZE (0x00010000)
-#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
-
/*
* Platform specific page table and MMU setup constants
*/
#define MAX_MMAP_REGIONS 16
-#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
-
/*
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
projects / project / bcm63xx / atf.git / commitdiff